A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven Engineering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to executable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of G. Ochoa-Ruiz ( ) · O. Labbani · E.-B. Bourennane LE2I Laboratory, Burgundy University, Dijon, France e-mail: [email protected] O. Labbani e-mail: [email protected] E.-B. Bourennane e-mail: [email protected] P. Soulard SODIUS, Nantes, France e-mail: [email protected] S. Cherif INRIA Lille Nord Europe, Villeneuve d’Ascq, France e-mail: [email protected] ha l-0 07 45 37 7, v er si on 1 31 O ct 2 01 2 Author manuscript, published in "Design Automation for Embedded Systems (2012)"